// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
module schedule_frame_cnt_interface(
    input  wire       clk                     , 
    input  wire       rst_n                   ,
    //******************************************************************
    //cpu_interface
    //******************************************************************
    //rx_tx_frame count
    input  wire [ 2:0]  queue_tx_frame_cnt_dpram_addr               ,
    //input  wire         queue_tx_frame_cnt_dpram_wen                ,
    //input  wire [31:0]  queue_tx_frame_cnt_dpram_wdata              ,
    input  wire         queue_tx_frame_cnt_dpram_ren                ,
    output reg  [31:0]  queue_tx_frame_cnt_dpram_rdata              ,

    input  wire [ 2:0]  queue_rx_frame_cnt_dpram_addr               ,
    //input  wire         queue_rx_frame_cnt_dpram_wen                ,
    //input  wire [31:0]  queue_rx_frame_cnt_dpram_wdata              ,
    input  wire         queue_rx_frame_cnt_dpram_ren                ,
    output reg  [31:0]  queue_rx_frame_cnt_dpram_rdata              ,
    
    //******************************************************************
    //queue_shedule interface
    //******************************************************************
    //rx_tx_frame count
    input  wire [31:0]  rx_frame_cnt_node_0             ,
    input  wire [31:0]  rx_frame_cnt_node_1             ,
    input  wire [31:0]  rx_frame_cnt_node_2             ,
    input  wire [31:0]  rx_frame_cnt_node_3             ,
    input  wire [31:0]  rx_frame_cnt_node_4             ,
    input  wire [31:0]  tx_frame_cnt_node_0             ,
    input  wire [31:0]  tx_frame_cnt_node_1             ,
    input  wire [31:0]  tx_frame_cnt_node_2             ,
    input  wire [31:0]  tx_frame_cnt_node_3             ,
    input  wire [31:0]  tx_frame_cnt_node_4              
    );


//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

//WIRES
wire [2:0] node_rd_rx_select;
wire [2:0] node_rd_tx_select;
 //*********************
//MAIN CORE
//*********************
assign node_rd_rx_select = (queue_rx_frame_cnt_dpram_ren)? queue_rx_frame_cnt_dpram_addr : 3'b111;
assign node_rd_tx_select = (queue_tx_frame_cnt_dpram_ren)? queue_tx_frame_cnt_dpram_addr : 3'b111;

always @(posedge clk or negedge rst_n) begin : read_rx_frame_cnt
    if (~rst_n) begin
        // reset
        queue_rx_frame_cnt_dpram_rdata <= 32'b0;
    end
    else if (node_rd_rx_select == 3'd0) begin
        queue_rx_frame_cnt_dpram_rdata <= rx_frame_cnt_node_0;
    end
    else if (node_rd_rx_select == 3'd1) begin
        queue_rx_frame_cnt_dpram_rdata <= rx_frame_cnt_node_1;
    end
    else if (node_rd_rx_select == 3'd2) begin
        queue_rx_frame_cnt_dpram_rdata <= rx_frame_cnt_node_2;
    end
    else if (node_rd_rx_select == 3'd3) begin
        queue_rx_frame_cnt_dpram_rdata <= rx_frame_cnt_node_3;
    end
    else if (node_rd_rx_select == 3'd4) begin
        queue_rx_frame_cnt_dpram_rdata <= rx_frame_cnt_node_4;
    end
    else begin
        queue_rx_frame_cnt_dpram_rdata <= queue_rx_frame_cnt_dpram_rdata;
    end
end

always @(posedge clk or negedge rst_n) begin : read_tx_frame_cnt
    if (~rst_n) begin
        // reset
        queue_tx_frame_cnt_dpram_rdata <= 32'b0;
    end
    else if (node_rd_tx_select == 3'd0) begin
        queue_tx_frame_cnt_dpram_rdata <= tx_frame_cnt_node_0;
    end
    else if (node_rd_tx_select == 3'd1) begin
        queue_tx_frame_cnt_dpram_rdata <= tx_frame_cnt_node_1;
    end
    else if (node_rd_tx_select == 3'd2) begin
        queue_tx_frame_cnt_dpram_rdata <= tx_frame_cnt_node_2;
    end
    else if (node_rd_tx_select == 3'd3) begin
        queue_tx_frame_cnt_dpram_rdata <= tx_frame_cnt_node_3;
    end
    else if (node_rd_tx_select == 3'd4) begin
        queue_tx_frame_cnt_dpram_rdata <= tx_frame_cnt_node_4;
    end
    else begin
        queue_tx_frame_cnt_dpram_rdata <= queue_tx_frame_cnt_dpram_rdata;
    end
end

endmodule
